| Artículo | 2024 |
NanoBoot: A Field-Programmable Gate Array/System-on-Chip Hardware Boot Loader for IoT Devices
|
ELECTRONICS |
| Ponencia | 2024 |
YASAC: Yet Another Simple Academic Computer and Teaching Methodology
|
16th Congreso de Tecnologia, Aprendizaje y Ensenanza de la Electronica, TAEE 2024 |
| Artículo | 2023 |
IRIS: an embedded secure boot for IoT devices
|
Internet of Things (Netherlands) |
| Ponencia | 2022 |
A methodological proposal for the digital electronics subject laboratory
|
2022 Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (XV Technologies Applied to Electronics Teaching Conference) |
| Capítulo | 2022 |
Entorno de virtualización para la realización y evaluación de prácticas de laboratorio TIC
|
Libro de actas TAEE 2022 XV Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica: Livro de procedimentos TAEE 2022 XV Conferência em Tecnologia, Aprendizagem e Ensino da Eletrónica=Proceedings book TAEE 2022 XV International Conference of Technology, Learning and Teaching of Electronics |
| Capítulo | 2022 |
Una propuesta metodológica para el laboratorio de asignaturas de Electrónica Digital
|
Libro de actas TAEE 2022 XV Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica: Livro de procedimentos TAEE 2022 XV Conferência em Tecnologia, Aprendizagem e Ensino da Eletrónica=Proceedings book TAEE 2022 XV International Conference of Technology, Learning and Teaching of Electronics |
| Ponencia | 2022 |
Virtualization environment for IT labs development and assessment
|
15th International Conference of Technology, Learning and Teaching of Electronics, TAEE 2022 - Proceedings |
| Artículo | 2021 |
An integrated digital system design framework with on-chip functional verification and performance evaluation
|
IEEE ACCESS |
| Artículo | 2021 |
Embedded LUKS (E-LUKS): a hardware solution to IoT security
|
ELECTRONICS |
| Artículo | 2020 |
Address-encoded byte order
|
MICROPROCESSORS AND MICROSYSTEMS |
| Ponencia | 2020 |
Experiencia en la adaptación de una asignatura de máster para su impartición completa a distancia
|
XIV Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica: Proceedings TAEE2020 = XIV Conferência em Tecnologias Aplicadas ao Ensino da Eletrónica = XIV Conference on Technology, Teaching and Learning of Electronics |
| Artículo | 2020 |
Using the complement of the cosine to compute trigonometric functions
|
EURASIP JOURNAL ON ADVANCES IN SIGNAL PROCESSING |
| Artículo | 2019 |
High-performance time server core for FPGA system-on-chip
|
ELECTRONICS |
| Artículo | 2017 |
Minimalistic SDHC-SPI hardware reader module for boot loader applications
|
MICROELECTRONICS JOURNAL |
| Capítulo | 2016 |
Metodología PBL en modo colaborativo aplicada al diseño de un SoC
|
Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE 2016): libro de Actas del XII Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica |
| Libro | 2016 |
Tecnología, Aprendizaje y Enseñanza de la Electrónica: TAEE 2016: Libro de Actas del XII Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica
|
Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE 2016): libro de Actas del XII Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica |
| Ponencia | 2015 |
EvercodeML: A formal language for SoC integration
|
Proceedings of the electronic system level synthesis conference |
| Artículo | 2013 |
NanoFS: a hardware-oriented file system
|
ELECTRONICS LETTERS |
| Ponencia | 2013 |
Network Time Synchronization: A Full Hardware Approach
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION |
| Capítulo | 2012 |
Experiencia de renovación metodológica en la enseñanza de la electrónica digital básica
|
Tecnologías Aplicadas en la Enseñanza de la Electrónica: TAEE 2012 : Actas del X Congreso de Tecnologías Aplicadas en la Enseñanza de la Electrónica, Escuela de Ingeniería Industrial Universidad de Vigo Vigo, España 13 al 15 Junio de 2012 |
| Artículo | 2012 |
Long-term on-chip verification of systems with logical events scattered in time
|
MICROPROCESSORS AND MICROSYSTEMS |
| Ponencia | 2012 |
Methodology updating experience in basic digital electronics teaching
|
Proceedings - 2012 Technologies Applied to Electronics Teaching, TAEE 2012 |
| Artículo | 2011 |
Fast-convergence microsecond-accurate clock discipline algorithm for hardware implementation
|
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT |
| Ponencia | 2011 |
Python as a hardware description language: A case study
|
Proceedings of the 2011 7th Southern Conference on Programmable Logic, SPL 2011 |
| Artículo | 2011 |
Studying the viability of static complementary metal-oxide-semiconductor gates with a large number of inputs when using separate transistor wells
|
JOURNAL OF LOW POWER ELECTRONICS |
| Artículo | 2010 |
Comprehensive analysis on the internal power dissipation of static CMOS cells in ultra-deep sub-micron technologies
|
JOURNAL OF LOW POWER ELECTRONICS |
| Ponencia | 2010 |
Design and implementation of a suitable core for on-chip long-term verification
|
2010 International Symposium on Industrial Embedded Systems, SIES 2010 - Conference Proceedings |
| Ponencia | 2009 |
Delay and power consumption of static Bulk-CMOS gates using independent bodies
|
DTIS: 2009 4TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA, PROCEEDINGS |
| Ponencia | 2009 |
EFFICIENT TECHNIQUES AND METHODOLOGIES FOR EMBEDDED SYSTEM DESIGN USIGN FREE HARDWARE AND OPEN STANDARDS
|
FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS |
| Ponencia | 2009 |
Implementación sobre FPGA de un cliente SNTP de bajo coste y alta precisión
|
Actas de las IX Jornadas de computación reconfigurable y aplicaciones: Universidad de Alcalá, Departamento de Electrónica, Alcalá de Henares, 9-11 septiembre, 2009 |
| Ponencia | 2009 |
Power dissipation associated to internal effect transitions in static CMOS gates
|
INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION |
| Ponencia | 2009 |
Usando Python como HDL: estudio comparativo de resultados basado en el desarrollo de un periférico real
|
Actas de las IX Jornadas de computación reconfigurable y aplicaciones: Universidad de Alcalá, Departamento de Electrónica, Alcalá de Henares, 9-11 septiembre, 2009 |
| Ponencia | 2008 |
Building a SoC for industrial applications based on LEON microprocessor and a GNU/Linux distribution
|
2008 IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS, VOLS 1-5 |
| Ponencia | 2008 |
Design and Implementation of a SNTP Client on FPGA
|
2008 IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS, VOLS 1-5 |
| Ponencia | 2008 |
Digital Data Processing peripheral design for an embedded application based on the MicroBlaze soft core
|
2008 4TH SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS |
| Ponencia | 2007 |
Automatic logic synthesis for parallel alternating latches clocking schemes
|
VLSI CIRCUITS AND SYSTEMS III |
| Ponencia | 2007 |
Design of a FFT/IFFT module as an IP core suitable for embedded systems
|
2007 INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS |
| Artículo | 2007 |
Improving the performance of static CMOS gates by using independent bodies
|
JOURNAL OF LOW POWER ELECTRONICS |
| Ponencia | 2007 |
Static power consumption in CMOS gates using independent bodies
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION |
| Ponencia | 2006 |
A SoC Design Methodology for LEON2 on FPGA
|
IWS 2006: XII Taller IBERCHIP (2006). |
| Artículo | 2006 |
Accurate Logic-Level Current Estimation for Digital CMOS Circuits
|
JOURNAL OF LOW POWER ELECTRONICS |
| Artículo | 2006 |
Automated performance evaluation of skew-tolerant clocking schemes
|
International Journal of Electronics |
| Ponencia | 2006 |
Efficient design and implementation on FPGA of a MicroBlaze peripheral for processing direct electrical networks measurements
|
Industrial Embedded Systems - IES'2006 |
| Ponencia | 2005 |
Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes
|
VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2 |
| Ponencia | 2005 |
Application of internode model to global power consumption estimation in SCMOS gates
|
Lecture Notes in Computer Science |
| Ponencia | 2005 |
Halotis - High accurate logic timing simulator
|
2005 PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS, VOLS 1 AND 2, PROCEEDINGS |
| Artículo | 2005 |
Logic-level fast current simulation for digital CMOS circuits
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN |
| Ponencia | 2005 |
Optimization techniques for dynamic behavior modeling of digital CMOS VLSI circuits in nanometric technologies
|
2005 PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS, VOLS 1 AND 2, PROCEEDINGS |
| Editorial | 2005 |
Power and timing modelling, optimisation and simulation
|
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES |
| Artículo | 2004 |
Signal sampling based transition modeling for digital gates characterization
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN |
| Artículo | 2003 |
Computational delay models to estimate the delay of floating cubes in CMOS circuits
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN |
| Ponencia | 2003 |
Internode: internal node logic computational model
|
36TH ANNUAL SIMULATION SYMPOSIUM, PROCEEDINGS |
| Ponencia | 2002 |
Characterization of normal propagation delay for delay degradation model (DDM)
|
Lecture Notes in Computer Science |
| Capítulo | 2002 |
Efficient and fast current curve estimation of CMOS digital circuits at the logic level
|
Integrated circuit design. Power and timing modeling, optimization and simulation: 12th International Workshop, PATMOS 2002, Seville, Spain, September 11 - 13, 2002 |
| Artículo | 2002 |
Measurement of the switching activity of CMOS digital circuits at the gate level
|
Lecture Notes in Computer Science |
| Ponencia | 2001 |
AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model
|
ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS |
| Ponencia | 2001 |
Gate-level simulation of CMOS circuits using the IDDM model
|
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings |
| Ponencia | 2001 |
HALOTIS: High Accuracy LOgic TIming Simulator with inertial and degradation delay model
|
DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS |
| Artículo | 2001 |
Switching activity evaluation of CMOS digital circuits using logic timing simulation
|
ELECTRONICS LETTERS |
| Artículo | 2000 |
Degradation delay model extension to CMOS gates
|
INTEGRATED CIRCUIT DESIGN, PROCEEDINGS |
| Ponencia | 2000 |
Inertial and Degradation Delay Model for CMOS logic gates
|
2000 IEEE International Symposium on Circuits and Systems (ISCAS) |
| Artículo | 2000 |
Influence of clocking strategies on the design of low switching-noise digital and mixed-signal VLSI circuits
|
INTEGRATED CIRCUIT DESIGN, PROCEEDINGS |
| Artículo | 2000 |
Logical modelling of delay degradation effect in static CMOS gates
|
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS |
| Libro | 2000 |
Temporización en circuitos integrados digitales CMOS
|
Temporización en circuitos integrados digitales CMOS |
| Artículo | 1999 |
Aprendiendo a diseñar circuitos integrados digitales mediante el uso del ordenador
|
Revista de Enseñanza Universitaria |
| Artículo | 1999 |
Inertial effect handling method for CMOS digital IC simulation
|
ELECTRONICS LETTERS |
| Artículo | 1997 |
Analysis of metastable operation in a CMOS dynamic D-latch
|
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING |
| Artículo | 1997 |
CMOS inverter maximum frequency of operation due to digital signal degradation
|
ELECTRONICS LETTERS |
