| Ponencia | 2024 |
Hardware Secure Boot. A Review Of ”IRIS: An Embedded Secure Boot for IoT devices”
|
IX Jornadas Nacionales de Investigación En Ciberseguridad |
| Ponencia | 2024 |
Metodología basada en proyectos para el desarrollo de sistemas IoT
|
XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE 2024). Libro de actas: XVI Conferência em Tecnologia, Aprendizagem e Ensino da Eletrónica (TAEE 2024). Livro de atas.XVI International Conference of Technology, Learning and Teaching of Electronics (TAEE 2024). Proceedings book |
| Artículo | 2024 |
NanoBoot: A Field-Programmable Gate Array/System-on-Chip Hardware Boot Loader for IoT Devices
|
ELECTRONICS |
| Artículo | 2023 |
IRIS: an embedded secure boot for IoT devices
|
Internet of Things (Netherlands) |
| Artículo | 2021 |
An integrated digital system design framework with on-chip functional verification and performance evaluation
|
IEEE ACCESS |
| Artículo | 2021 |
Embedded LUKS (E-LUKS): a hardware solution to IoT security
|
ELECTRONICS |
| Artículo | 2020 |
Address-encoded byte order
|
MICROPROCESSORS AND MICROSYSTEMS |
| Artículo | 2020 |
Using the complement of the cosine to compute trigonometric functions
|
EURASIP JOURNAL ON ADVANCES IN SIGNAL PROCESSING |
| Artículo | 2019 |
High-performance time server core for FPGA system-on-chip
|
ELECTRONICS |
| Artículo | 2017 |
Minimalistic SDHC-SPI hardware reader module for boot loader applications
|
MICROELECTRONICS JOURNAL |
| Ponencia | 2016 |
Building a basic membrane computer
|
Fourteenth Brainstorming Week on Membrane Computing |
| Artículo | 2016 |
Fast hardware implementations of static P systems
|
COMPUTING AND INFORMATICS |
| Capítulo | 2016 |
Metodología PBL en modo colaborativo aplicada al diseño de un SoC
|
Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE 2016): libro de Actas del XII Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica |
| Ponencia | 2015 |
EvercodeML: A formal language for SoC integration
|
Proceedings of the electronic system level synthesis conference |
| Artículo | 2013 |
NanoFS: a hardware-oriented file system
|
ELECTRONICS LETTERS |
| Ponencia | 2013 |
Network Time Synchronization: A Full Hardware Approach
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION |
| Capítulo | 2012 |
Open Development Platform for Embedded Systems
|
Grid Computing - Technology and Applications, Widespread Coverage and New Horizons |
| Artículo | 2011 |
Fast-convergence microsecond-accurate clock discipline algorithm for hardware implementation
|
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT |
| Ponencia | 2011 |
Python as a hardware description language: A case study
|
Proceedings of the 2011 7th Southern Conference on Programmable Logic, SPL 2011 |
| Artículo | 2011 |
Studying the viability of static complementary metal-oxide-semiconductor gates with a large number of inputs when using separate transistor wells
|
JOURNAL OF LOW POWER ELECTRONICS |
| Artículo | 2010 |
Comprehensive analysis on the internal power dissipation of static CMOS cells in ultra-deep sub-micron technologies
|
JOURNAL OF LOW POWER ELECTRONICS |
| Ponencia | 2010 |
Design and implementation of a suitable core for on-chip long-term verification
|
2010 International Symposium on Industrial Embedded Systems, SIES 2010 - Conference Proceedings |
| Ponencia | 2009 |
Aplicación de Picoblaze como emulador/receptor de un GPS en el diseño de hardware de un cliente/servidor SNTP
|
Actas de las IX Jornadas de computación reconfigurable y aplicaciones: Universidad de Alcalá, Departamento de Electrónica, Alcalá de Henares, 9-11 septiembre, 2009 |
| Ponencia | 2009 |
Delay and power consumption of static Bulk-CMOS gates using independent bodies
|
DTIS: 2009 4TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA, PROCEEDINGS |
| Ponencia | 2009 |
EFFICIENT TECHNIQUES AND METHODOLOGIES FOR EMBEDDED SYSTEM DESIGN USIGN FREE HARDWARE AND OPEN STANDARDS
|
FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS |
| Ponencia | 2009 |
Power dissipation associated to internal effect transitions in static CMOS gates
|
INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION |
| Ponencia | 2009 |
Usando Python como HDL: estudio comparativo de resultados basado en el desarrollo de un periférico real
|
Actas de las IX Jornadas de computación reconfigurable y aplicaciones: Universidad de Alcalá, Departamento de Electrónica, Alcalá de Henares, 9-11 septiembre, 2009 |
| Ponencia | 2008 |
Building a SoC for industrial applications based on LEON microprocessor and a GNU/Linux distribution
|
2008 IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS, VOLS 1-5 |
| Ponencia | 2008 |
Design and Implementation of a SNTP Client on FPGA
|
2008 IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS, VOLS 1-5 |
| Ponencia | 2008 |
Digital Data Processing peripheral design for an embedded application based on the MicroBlaze soft core
|
2008 4TH SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS |
| Ponencia | 2008 |
Implementation of a FFT/IFFT module on FPGA: comparison of methodologies
|
2008 4TH SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS |
| Ponencia | 2007 |
Automatic logic synthesis for parallel alternating latches clocking schemes
|
VLSI CIRCUITS AND SYSTEMS III |
| Ponencia | 2007 |
Design of a FFT/IFFT module as an IP core suitable for embedded systems
|
2007 INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS |
| Artículo | 2007 |
Improving the performance of static CMOS gates by using independent bodies
|
JOURNAL OF LOW POWER ELECTRONICS |
| Ponencia | 2007 |
Static power consumption in CMOS gates using independent bodies
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION |
| Ponencia | 2006 |
A SoC Design Methodology for LEON2 on FPGA
|
IWS 2006: XII Taller IBERCHIP (2006). |
| Artículo | 2006 |
Accurate Logic-Level Current Estimation for Digital CMOS Circuits
|
JOURNAL OF LOW POWER ELECTRONICS |
| Artículo | 2006 |
Automated performance evaluation of skew-tolerant clocking schemes
|
International Journal of Electronics |
| Ponencia | 2006 |
Efficient design and implementation on FPGA of a MicroBlaze peripheral for processing direct electrical networks measurements
|
Industrial Embedded Systems - IES'2006 |
| Ponencia | 2005 |
Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes
|
VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2 |
| Ponencia | 2005 |
Halotis - High accurate logic timing simulator
|
2005 PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS, VOLS 1 AND 2, PROCEEDINGS |
| Ponencia | 2005 |
Optimization techniques for dynamic behavior modeling of digital CMOS VLSI circuits in nanometric technologies
|
2005 PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS, VOLS 1 AND 2, PROCEEDINGS |
| Artículo | 2004 |
Signal sampling based transition modeling for digital gates characterization
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN |
| Artículo | 2003 |
Computational delay models to estimate the delay of floating cubes in CMOS circuits
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN |
| Ponencia | 2003 |
Internode: internal node logic computational model
|
36TH ANNUAL SIMULATION SYMPOSIUM, PROCEEDINGS |
| Ponencia | 2002 |
Characterization of normal propagation delay for delay degradation model (DDM)
|
Lecture Notes in Computer Science |
| Capítulo | 2002 |
Efficient and fast current curve estimation of CMOS digital circuits at the logic level
|
Integrated circuit design. Power and timing modeling, optimization and simulation: 12th International Workshop, PATMOS 2002, Seville, Spain, September 11 - 13, 2002 |
| Artículo | 2002 |
Measurement of the switching activity of CMOS digital circuits at the gate level
|
Lecture Notes in Computer Science |
| Ponencia | 2001 |
AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model
|
ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS |
| Ponencia | 2001 |
Gate-level simulation of CMOS circuits using the IDDM model
|
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings |
| Ponencia | 2001 |
HALOTIS: High Accuracy LOgic TIming Simulator with inertial and degradation delay model
|
DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS |
| Artículo | 2001 |
Switching activity evaluation of CMOS digital circuits using logic timing simulation
|
ELECTRONICS LETTERS |
| Artículo | 2000 |
Degradation delay model extension to CMOS gates
|
INTEGRATED CIRCUIT DESIGN, PROCEEDINGS |
| Ponencia | 2000 |
Inertial and Degradation Delay Model for CMOS logic gates
|
2000 IEEE International Symposium on Circuits and Systems (ISCAS) |
| Artículo | 2000 |
Influence of clocking strategies on the design of low switching-noise digital and mixed-signal VLSI circuits
|
INTEGRATED CIRCUIT DESIGN, PROCEEDINGS |
| Artículo | 2000 |
Logical modelling of delay degradation effect in static CMOS gates
|
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS |
| Libro | 2000 |
Temporización en circuitos integrados digitales CMOS
|
Temporización en circuitos integrados digitales CMOS |
| Artículo | 1999 |
Aprendiendo a diseñar circuitos integrados digitales mediante el uso del ordenador
|
Revista de Enseñanza Universitaria |
| Artículo | 1999 |
Inertial effect handling method for CMOS digital IC simulation
|
ELECTRONICS LETTERS |
| Artículo | 1998 |
Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure
|
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS |
| Artículo | 1998 |
Efficient self-timed circuits based on weak NMOS-trees
|
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems |
| Artículo | 1997 |
Analysis of metastable operation in a CMOS dynamic D-latch
|
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING |
| Artículo | 1997 |
CMOS inverter maximum frequency of operation due to digital signal degradation
|
ELECTRONICS LETTERS |
| Ponencia | 1996 |
Multimedia system for instruction and learning electronics
|
Lecture Notes in Computer Science |
| Artículo | 1995 |
Evaluation of metastability transfer models - an application to an n-bistable CMOS synchronizer
|
International Journal of Electronics |
| Nota | 1995 |
Modular asynchronous arbiter insensitive to metastability
|
IEEE TRANSACTIONS ON COMPUTERS |
| Ponencia | 1995 |
New CMOS VLSI linear self-timed architectures
|
SECOND WORKING CONFERENCE ON ASYNCHRONOUS DESIGN METHODOLOGIES, PROCEEDINGS |
| Nota | 1995 |
SODS - a new cmos differential-type structure
|
IEEE JOURNAL OF SOLID-STATE CIRCUITS |
| Ponencia | 1994 |
Implementación de FIFOs mediante arquitecturas lineales autotemporizadas VLSI
|
Actas del IX Congreso de Diseño de Circuitos Integrados, 9, 10 y 11 de noviembre de 1994, Maspalomas, Gran Canaria |
| Ponencia | 1994 |
Modelos de retraso dinámicos para puertas estáticas CMOS: (basados en la propagación de pulsos)
|
Actas del IX Congreso de Diseño de Circuitos Integrados, 9, 10 y 11 de noviembre de 1994, Maspalomas, Gran Canaria |
| Ponencia | 1993 |
A new faster method for calculating the resolution coefficient of CMOS latches: Design of an optimum latch
|
1993 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS : PROCEEDINGS, VOLS 1-4 ( ISCAS 93 ) |
| Artículo | 1993 |
Arquitectura para el diseño de circuitos autotemporizados bidimensionales. Realización de multiplicadores
|
VIII Congreso Diseño de Circuitos Integrados: Málaga, 9 al 11 de noviembre de 1993 |
| Artículo | 1993 |
Design, testing and applications of 4-valued pads
|
International Journal of Electronics |
| Ponencia | 1993 |
Fully Digital Redundant Random Number Generator in CMOS Technology
|
ESSCIRC '93: NINETEENTH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS |
| Ponencia | 1993 |
Modeling of real bistables in VHDL
|
EURO-DAC 93 - EUROPEAN DESIGN AUTOMATION CONFERENCE WITH EURO-VHDL 93 : PROCEEDINGS |
| Artículo | 1993 |
Un nuevo modelo de retraso para puertas lógicas CMOS
|
VIII Congreso Diseño de Circuitos Integrados: Málaga, 9 al 11 de noviembre de 1993 |
| Ponencia | 1993 |
Workbench for generation of component models
|
European Design Automation Conference - Proceedings |
| Ponencia | 1992 |
A simple binary random number generator: new approaches for CMOS VLSI
|
PROCEEDINGS OF THE 35TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 |
| Ponencia | 1992 |
Determinación de coeficienta de resolución en biestables RS CMOS
|
VII Congreso de Diseño de Circuitos Integrados: 3, 4 y 5 de noviembre de 1992, Toledo, España : actas |
| Artículo | 1992 |
Multiple-valued pads for binary chips
|
ELECTRONICS LETTERS |
| Artículo | 1992 |
Simple binary random number generator
|
ELECTRONICS LETTERS |
| Ponencia | 1991 |
Diseño de un generador aleatorio de bit
|
Diseño de circuitos integrados: actas del VI Congreso, Santander, 11/15 de noviembre de 1991 |
