| Ponencia | 2024 |
Aprendizaje de diseño digital basado en proyectos:: Uso de leds RGB
|
XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE 2024). Libro de actas: XVI Conferência em Tecnologia, Aprendizagem e Ensino da Eletrónica (TAEE 2024). Livro de atas.XVI International Conference of Technology, Learning and Teaching of Electronics (TAEE 2024). Proceedings book |
| Capítulo | 2024 |
Auto-tuning System for Maximum Operating Frequency in FPGA by Dynamic Reconfiguration
|
Springer Proceedings in Materials |
| Ponencia | 2024 |
Project-based learning of digital design: Using RGB LEDs
|
16th Congreso de Tecnologia, Aprendizaje y Ensenanza de la Electronica, TAEE 2024 |
| Capítulo | 2022 |
Diseño de probador de ICs y su efecto en la aplicación en laboratorios de electrónica ́
|
Libro de actas TAEE 2022 XV Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica: Livro de procedimentos TAEE 2022 XV Conferência em Tecnologia, Aprendizagem e Ensino da Eletrónica=Proceedings book TAEE 2022 XV International Conference of Technology, Learning and Teaching of Electronics |
| Capítulo | 2022 |
Enseñanza basada en diseños propuestos por los alumnos: caso práctico
|
Libro de actas TAEE 2022 XV Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica: Livro de procedimentos TAEE 2022 XV Conferência em Tecnologia, Aprendizagem e Ensino da Eletrónica=Proceedings book TAEE 2022 XV International Conference of Technology, Learning and Teaching of Electronics |
| Ponencia | 2022 |
ICs tester design and its effect on application in electronics laboratories
|
15th International Conference of Technology, Learning and Teaching of Electronics, TAEE 2022 - Proceedings |
| Ponencia | 2022 |
Teaching based on proposed by students designs: a case study
|
15th International Conference of Technology, Learning and Teaching of Electronics, TAEE 2022 - Proceedings |
| Artículo | 2021 |
Experimental FIA methodology using clock and control signal modifications under power supply and temperature variations
|
SENSORS |
| Artículo | 2021 |
Trivium stream cipher countermeasures against fault injection attacks and DFA
|
IEEE ACCESS |
| Artículo | 2020 |
An academic approach to FPGA design based on a distance meter circuit
|
IEEE REVISTA IBEROAMERICANA DE TECNOLOGIAS DEL APRENDIZAJE-IEEE RITA |
| Artículo | 2020 |
ASIC design and power characterization of standard and low power multi-radix trivium
|
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS |
| Artículo | 2020 |
Breaking trivium stream cipher implemented in ASIC using experimental attacks and DFA
|
SENSORS |
| Ponencia | 2020 |
Desarrollo de un juego sobre FPGA mediante trabajo en equipo
|
XIV Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica: Proceedings TAEE2020 = XIV Conferência em Tecnologias Aplicadas ao Ensino da Eletrónica = XIV Conference on Technology, Teaching and Learning of Electronics |
| Ponencia | 2020 |
Hamming-code based fault detection design methodology for block ciphers
|
Proceedings - IEEE International Symposium on Circuits and Systems |
| Ponencia | 2020 |
Learning VHDL through teamwork FPGA game design
|
Proceedings - 2020 14th Technologies Applied to Electronics Teaching Conference, TAEE 2020 |
| Ponencia | 2019 |
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher
|
Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018 |
| Ponencia | 2018 |
Distance measurement as a practical example of FPGA design
|
2018 XIII TECHNOLOGIES APPLIED TO ELECTRONICS TEACHING CONFERENCE (TAEE) |
| Ponencia | 2018 |
Ejemplo de diseño FPGA para medidas de máximas frecuencias de operación
|
Tecnología, Aprendizaje y Enseñanza de la Electrónica : Actas del XIII Congreso de Tecnología, Aprendizaje y Enseñanzade la Electrónica, Tenerife, 20-22 de junio, 2018 |
| Ponencia | 2018 |
FPGA design example for maximum operating frequency measurements
|
2018 XIII TECHNOLOGIES APPLIED TO ELECTRONICS TEACHING CONFERENCE (TAEE) |
| Ponencia | 2018 |
Medición de distancias como ejemplo práctico de diseño en FPGAs
|
Tecnología, Aprendizaje y Enseñanza de la Electrónica : Actas del XIII Congreso de Tecnología, Aprendizaje y Enseñanzade la Electrónica, Tenerife, 20-22 de junio, 2018 |
| Ponencia | 2017 |
Experimental and timing analysis comparison of FPGA trivium implementations and their vulnerability to clock fault injection
|
2016 Conference on Design of Circuits and Integrated Systems, DCIS 2016 - Proceedings |
| Artículo | 2017 |
Multiradix trivium implementations for low-power IoT hardware
|
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
| Artículo | 2017 |
Trivium hardware implementations for power reduction
|
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS |
| Artículo | 2017 |
Vulnerability analysis of trivium FPGA implementations
|
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS |
| Ponencia | 2016 |
Creating helping posters for electronic labs
|
Proceedings of 2016 Technologies Applied to Electronics Teaching, TAEE 2016 |
| Ponencia | 2016 |
Diseño de circuitos integrados y seguridad de circuitos criptográficos frente a ataques
|
III Jornada de investigación y postgrado: Libro de Actas |
| Ponencia | 2016 |
Educational applications of a pico-processor design
|
Proceedings of 2016 Technologies Applied to Electronics Teaching, TAEE 2016 |
| Ponencia | 2016 |
Fault attack on FPGA implementations of Trivium stream cipher
|
2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
| Ponencia | 2016 |
Fault injection on FPGA implementations of trivium stream cipher using clock attacks
|
TRUDEVICE 2016: 6th Conference on Trustworthy Manufacturing and Utilization of Secure Devices (2016). |
| Ponencia | 2014 |
A message transmission system with lightweight encryption as a project in a Master subject
|
Proceedings of XI Tecnologias Aplicadas a la Ensenanza de la Electronica (Technologies Applied to Electronics Teaching), TAEE 2014 |
| Ponencia | 2013 |
Low power implementation of Trivium stream cipher
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION |
| Ponencia | 2010 |
High Radix Implementation of Montgomery Multipliers with CSA
|
2010 INTERNATIONAL CONFERENCE ON MICROELECTRONICS |
| Ponencia | 2010 |
Innovative learning and teaching methodology in electronic technology area: A case of study in computer science university degrees
|
2010 IEEE Education Engineering Conference, EDUCON 2010 |
| Ponencia | 2010 |
Metodología orientada a la elección de FPGAs con prioridad en el consumo de potencia
|
16th Workshop Iberchip (2010) (2010), pp. 161185949. |
| Artículo | 2009 |
Estudio comparativo de los divisores en la tecnologías CMOS nanométricas
|
Revista de Ingeniería Electrónica, Automática y Comunicaciones |
| Ponencia | 2008 |
Evaluación Continua: Una Experiencia Real en Asignatura de Primer Curso
|
Libro de Resúmenes: XVI Congreso Universitario de Innovación Educativa en las Enseñanzas Técnicas Cádiz, 23 al 26 de de Septiembre 2008 |
| Ponencia | 2007 |
A switching noise vision of the optimization techniques for low-power synthesis
|
2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3 |
| Ponencia | 2007 |
HEAPAN: a high level computer architecture analysis tool
|
VLSI CIRCUITS AND SYSTEMS III |
| Capítulo | 2007 |
Logic Synthesis
|
Wiley Encyclopedia of Computer Science and Engineering |
| Ponencia | 2007 |
Partitioning and characterization of high speed adder structures in deep-submicron technologies
|
VLSI CIRCUITS AND SYSTEMS III |
| Capítulo | 2006 |
Fundamentals of timing simulation
|
Logic-Timing Simulation and the Degradation Delay Model |
| Ponencia | 2005 |
A methodology for the characterization of arithmetic circuits on CMOS deep submicron technologies
|
VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2 |
| Ponencia | 2005 |
Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits
|
VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2 |
| Capítulo | 2005 |
Formación de profesores noveles en tecnología electrónica: una primera aproximación
|
La formación del profesorado universitario: programa de equipos docentes de la Universidad de Sevilla, curso 2003-2004 |
| Artículo | 2005 |
Selective Clock-Gating for Low-Power Synchronous Counters
|
JOURNAL OF LOW POWER ELECTRONICS |
| Ponencia | 2003 |
Switching noise reduction in clock distribution in mixed-mode VLSI circuits
|
VLSI CIRCUITS AND SYSTEMS |
| Artículo | 2002 |
Measurement of the switching activity of CMOS digital circuits at the gate level
|
Lecture Notes in Computer Science |
| Artículo | 2002 |
Selective clock-gating for low power/low noise synchronous counters
|
Lecture Notes in Computer Science |
| Ponencia | 2001 |
AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model
|
ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS |
| Ponencia | 2001 |
Gate-level simulation of CMOS circuits using the IDDM model
|
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings |
| Ponencia | 2001 |
HALOTIS: High Accuracy LOgic TIming Simulator with inertial and degradation delay model
|
DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS |
| Artículo | 2001 |
Switching activity evaluation of CMOS digital circuits using logic timing simulation
|
ELECTRONICS LETTERS |
| Artículo | 2000 |
Degradation delay model extension to CMOS gates
|
INTEGRATED CIRCUIT DESIGN, PROCEEDINGS |
| Ponencia | 2000 |
Inertial and Degradation Delay Model for CMOS logic gates
|
2000 IEEE International Symposium on Circuits and Systems (ISCAS) |
| Artículo | 2000 |
Influence of clocking strategies on the design of low switching-noise digital and mixed-signal VLSI circuits
|
INTEGRATED CIRCUIT DESIGN, PROCEEDINGS |
| Artículo | 2000 |
Logical modelling of delay degradation effect in static CMOS gates
|
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS |
| Libro | 2000 |
Temporización en circuitos integrados digitales CMOS
|
Temporización en circuitos integrados digitales CMOS |
| Artículo | 1999 |
Inertial effect handling method for CMOS digital IC simulation
|
ELECTRONICS LETTERS |
| Artículo | 1998 |
Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure
|
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS |
| Artículo | 1998 |
Efficient self-timed circuits based on weak NMOS-trees
|
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems |
| Artículo | 1997 |
Analysis of metastable operation in a CMOS dynamic D-latch
|
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING |
| Artículo | 1997 |
CMOS inverter maximum frequency of operation due to digital signal degradation
|
ELECTRONICS LETTERS |
| Artículo | 1995 |
Evaluation of metastability transfer models - an application to an n-bistable CMOS synchronizer
|
International Journal of Electronics |
| Nota | 1995 |
Modular asynchronous arbiter insensitive to metastability
|
IEEE TRANSACTIONS ON COMPUTERS |
| Ponencia | 1995 |
New CMOS VLSI linear self-timed architectures
|
SECOND WORKING CONFERENCE ON ASYNCHRONOUS DESIGN METHODOLOGIES, PROCEEDINGS |
| Nota | 1995 |
SODS - a new cmos differential-type structure
|
IEEE JOURNAL OF SOLID-STATE CIRCUITS |
| Ponencia | 1994 |
Implementación de FIFOs mediante arquitecturas lineales autotemporizadas VLSI
|
Actas del IX Congreso de Diseño de Circuitos Integrados, 9, 10 y 11 de noviembre de 1994, Maspalomas, Gran Canaria |
| Ponencia | 1994 |
Modelos de retraso dinámicos para puertas estáticas CMOS: (basados en la propagación de pulsos)
|
Actas del IX Congreso de Diseño de Circuitos Integrados, 9, 10 y 11 de noviembre de 1994, Maspalomas, Gran Canaria |
| Ponencia | 1993 |
A new faster method for calculating the resolution coefficient of CMOS latches: Design of an optimum latch
|
1993 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS : PROCEEDINGS, VOLS 1-4 ( ISCAS 93 ) |
| Artículo | 1993 |
Arquitectura para el diseño de circuitos autotemporizados bidimensionales. Realización de multiplicadores
|
VIII Congreso Diseño de Circuitos Integrados: Málaga, 9 al 11 de noviembre de 1993 |
| Artículo | 1993 |
Design, testing and applications of 4-valued pads
|
International Journal of Electronics |
| Ponencia | 1993 |
Fully Digital Redundant Random Number Generator in CMOS Technology
|
ESSCIRC '93: NINETEENTH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS |
| Ponencia | 1993 |
Modeling of real bistables in VHDL
|
EURO-DAC 93 - EUROPEAN DESIGN AUTOMATION CONFERENCE WITH EURO-VHDL 93 : PROCEEDINGS |
| Artículo | 1993 |
Un nuevo modelo de retraso para puertas lógicas CMOS
|
VIII Congreso Diseño de Circuitos Integrados: Málaga, 9 al 11 de noviembre de 1993 |
| Ponencia | 1993 |
Workbench for generation of component models
|
European Design Automation Conference - Proceedings |
| Ponencia | 1992 |
A simple binary random number generator: new approaches for CMOS VLSI
|
PROCEEDINGS OF THE 35TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 |
| Ponencia | 1992 |
Determinación de coeficienta de resolución en biestables RS CMOS
|
VII Congreso de Diseño de Circuitos Integrados: 3, 4 y 5 de noviembre de 1992, Toledo, España : actas |
| Artículo | 1992 |
Multiple-valued pads for binary chips
|
ELECTRONICS LETTERS |
| Artículo | 1992 |
Redes de interconexión de procesadores con capacidad de tolerancia a fallos
|
VII Congreso de Diseño de Circuitos Integrados: 3, 4 y 5 de noviembre de 1992, Toledo, España : actas |
| Artículo | 1992 |
Simple binary random number generator
|
ELECTRONICS LETTERS |
| Ponencia | 1991 |
Diseño de un generador aleatorio de bit
|
Diseño de circuitos integrados: actas del VI Congreso, Santander, 11/15 de noviembre de 1991 |
| Ponencia | 1991 |
Diseño de una familia de pads
|
Diseño de circuitos integrados: actas del VI Congreso, Santander, 11/15 de noviembre de 1991 |
| Artículo | 1991 |
METASTABLE OPERATION IN RS FLIP FLOPS
|
International Journal of Electronics |
