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Ver Investigador - - Prisma - Unidad de Bibliometría

José María Quintana Toledo

Catedrático de Universidad
jmquintana@us.es
Área de conocimiento: Electrónica
Departamento: Electrónica y Electromagnetismo
Grupo: DISEÑO Y TEST DE CIRCUITOS INTEGRADOS DE SEÑAL MIXTA - TIC-178 (Universidad de Sevilla)
Centro mixto: Instituto de Microelectrónica de Sevilla (IMSE)
Prog. doctorado: CIENCIAS Y TECNOLOGÍAS FÍSICAS

Investiga en

Palabras clave
Líneas de investigación
Resumen
Tipo Año Título Fuente
Corrección2024 Reference values of EORTC QLQ-C30, EORTC QLQ-BR23, and EQ-5D-5L for women with non-metastatic breast cancer at diagnosis and 2 years after (vol 32, pg 989, 2023) QUALITY OF LIFE RESEARCH
Artículo2021 Insights into the dynamics of coupled VO2 oscillators for ONNs IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Artículo2021 Oscillatory neural networks using VO2 based phase encoded logic FRONTIERS IN NEUROSCIENCE
Artículo2020 Phase transition device for phase storing IEEE TRANSACTIONS ON NANOTECHNOLOGY
Artículo2014 Experimental validation of a two-phase clock scheme for fine-grained pipelined circuits based on monostable to bistable logic elements IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Ponencia2013 Novel dynamic gate topology for superpipelines in DSM technologies 16TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2013)
Artículo2013 Novel pipeline architectures based on Negative Differential Resistance devices MICROELECTRONICS JOURNAL
Ponencia2013 Synchronization of Optically Coupled Resonant Tunneling Diode Oscillators 8TH IBEROAMERICAN OPTICS MEETING AND 11TH LATIN AMERICAN MEETING ON OPTICS, LASERS, AND APPLICATIONS
Ponencia2013 Two-phase MOBILE interconnection schemes for ultra-grain pipeline applications INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION
Ponencia2012 Bifurcation diagrams in MOS-NDR frequency divider circuits 2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Ponencia2012 Compact and power efficient MOS-NDR Muller C-elements TECHNOLOGICAL INNOVATION FOR VALUE CREATION
Artículo2012 Domino inspired MOBILE networks ELECTRONICS LETTERS
Artículo2012 Two-phase RTD-CMOS pipelined circuits IEEE TRANSACTIONS ON NANOTECHNOLOGY
Ponencia2011 Efficient realization of RTD-CMOS logic gates Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Ponencia2011 Evaluation of MOBILE-based gate-level pipelining augmenting CMOS with RTDs VLSI CIRCUITS AND SYSTEMS V
Artículo2011 Improved Nanopipelined RTD Adder Using Generalized Threshold Gates IEEE TRANSACTIONS ON NANOTECHNOLOGY
Artículo2011 RTD-CMOS pipelined networks for reduced power consumption IEEE TRANSACTIONS ON NANOTECHNOLOGY
Artículo2011 Simplified single-phase clock scheme for MOBILE networks ELECTRONICS LETTERS
Ponencia2010 Evaluation of RTD-CMOS logic gates 13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS
Ponencia2010 Redes MOBILE MOS-NDR operando con reloj de una fase XVI Workshop Iberchip (2010), p 1-4
Ponencia2010 Single phase MOS-NDR MOBILE networks 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
Artículo2009 Efficient realisation of MOS-NDR threshold logic gates ELECTRONICS LETTERS
Ponencia2009 Fast and area efficient multi-input Muller C-element based on MOS-NDR ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5
Artículo2009 Operation limits for RTD-based MOBILE circuits IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Ponencia2008 A novel contribution to the RTD-based threshold logic family PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10
Ponencia2008 Analysis of the critical rise time in MOBILE-based circuits Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Ponencia2008 Design of RTD-based NMIN/NMAX gates 2008 8th IEEE Conference on Nanotechnology, IEEE-NANO
Ponencia2008 Limits to a correct operation in RTD-based ternary inverters PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10
Ponencia2008 Observation of Frequency Division and Chaos Behavior in a Laser Diode driven by a Resonant Tunneling Diode 2008 CONFERENCE ON LASERS AND ELECTRO-OPTICS & QUANTUM ELECTRONICS AND LASER SCIENCE CONFERENCE, VOLS 1-9
Ponencia2008 RTD based logic circuits using generalized threshold gates XXIII Conference Design of Circuits and Integrated Systems (2008)
Artículo2008 Synchronisation and chaos in a laser diode driven by a resonant tunnelling diode IET OPTOELECTRONICS
Artículo2008 Using multi-threshold threshold gates in RTD-based logic design: A case study MICROELECTRONICS JOURNAL
Ponencia2007 A quasi-differential quantizer based on SMOBILE SBCCI2007: 20TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN
Ponencia2007 Correct DC operation in RTD-based ternary inverters 2007 2ND IEEE INTERNATIONAL CONFERENCE ON NANO/MICRO ENGINEERED AND MOLECULAR SYSTEMS, VOLS 1-3
Ponencia2007 Correct operation in SMOBILE-based quasi-differential quantizers 2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3
Ponencia2007 Holding Dissapearance in RTD-based Quantizers European Nano Systems Worshop (2007)
Ponencia2007 Holding preserving in RTD-based multiple-valued quantizers 2007 7TH IEEE CONFERENCE ON NANOTECHNOLOGY, VOL 1-3
Ponencia2007 Limits to a correct evaluation in RTD-based ternary inverters 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3
Ponencia2007 Non return mobile logic family 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11
Ponencia2007 Operation Limits in RTD-based Ternary Quantizers GLSVLSI'07: PROCEEDINGS OF THE 2007 ACM GREAT LAKES SYMPOSIUM ON VLSI
Ponencia2007 Using multi-threshold threshold gates in rtd-based logic design. A case study European Nano Systems Worshop (2007)
Ponencia2006 DC correct operation in MOBILE inverters IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II
Ponencia2006 Design guides for a correct DC operation in RTD-based threshold gates DSD 2006: 9TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS
Artículo2006 Increased logic functionality of clocked series-connected RTDS IEEE TRANSACTIONS ON NANOTECHNOLOGY
Ponencia2006 Limits to a correct evaluation in RTD-based ternary inverters Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Ponencia2006 Monostable-bistable transition logic elements: Threshold logic vs. Boolean logic comparison 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3
Ponencia2006 Operation limits for MOBILE followers 2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006
Ponencia2006 Self-latching operation limits for MOBILE circuits 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS
Artículo2006 Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Artículo2006 Single phase clock scheme for mobile logic gates ELECTRONICS LETTERS
Artículo2005 Analysis of frequency divider RTD circuits IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Ponencia2005 Logic models supporting the design of MOBILE-based RTD circuits 16TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURE AND PROCESSORS, PROCEEDINGS
Ponencia2005 New circuit topology for logic gates based on RTDs 2005 5th IEEE Conference on Nanotechnology
Ponencia2005 Novel improved RTD-based implementation of multi-threshold logic gates 2005 PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS, VOLS 1 AND 2, PROCEEDINGS
Ponencia2005 Robust frequency divider based on resonant tunneling devices 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS
Artículo2005 Transistor critical sizing in MOBILE follower ELECTRONICS LETTERS
Artículo2004 A practical parallel architecture for stacks filters JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
Ponencia2004 A threshold logic synthesis tool for RTD circuits PROCEEDINGS OF THE EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN
Artículo2004 Nonlinear dynamics in frequency divider RTD circuits ELECTRONICS LETTERS
Artículo2004 Pass-transistor based implementations of threshold logic gates for WOS filtering MICROELECTRONICS JOURNAL
Ponencia2004 Programmable logic gate based on resonant tunneling devices 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS
Ponencia2004 RTD-based compact programmable gates 2004 IEEE INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOLS 1-4, PROCEEDINGS
Artículo2004 Simplified Reed-Muller expressions for residue threshold functions CIRCUITS SYSTEMS AND SIGNAL PROCESSING
Ponencia2004 Useful logic blocks based on clocked series-connected RTDs 2004 4TH IEEE CONFERENCE ON NANOTECHNOLOGY
Artículo2004 Weighted order statistics filter for real-time signal processing applications based on pass transistor logic IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS
Ponencia2003 A LP-LV high performance monolitic DTMF receiver with on-chip test facilities VLSI CIRCUITS AND SYSTEMS
Ponencia2003 Design of residue generators using threshold logic PROCEEDINGS OF THE 46TH IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS & SYSTEMS, VOLS 1-3
Ponencia2003 Differential implementations of threshold logic gates SCS 2003: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS
Artículo2003 Multi-threshold threshold logic circuit design using resonant tunnelling devices ELECTRONICS LETTERS
Artículo2003 Review of capacitive threshold gate implementations ARTIFICIAL NEURAL NETWORKS AND NEURAL INFORMATION PROCESSING - ICAN/ICONIP 2003
Ponencia2003 Review of differential threshold gate implementations Proceedings of the IASTED International Conference on Neural Networks and Computational Intelligence
Ponencia2003 Threshold logic: From vacuum tubes to nanoelectronics PROCEEDINGS OF THE 46TH IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS & SYSTEMS, VOLS 1-3
Revisión2003 VLSI implementations of threshold logic - A comprehensive survey IEEE TRANSACTIONS ON NEURAL NETWORKS
Ponencia2002 An encoding technique for low power CMOS implementations of controllers DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS
Artículo2002 COPAS: A new algorithm for the partial input encoding problem VLSI DESIGN
Ponencia2002 High-speed low-power logic gates using floating gates 2002 IEEE International Symposium on Circuits and Systems (ISCAS)
Ponencia2002 Simple parallel weighted order statistic filter implementations 2002 IEEE International Symposium on Circuits and Systems (ISCAS)
Ponencia2002 Simplified Reed-Muller expressions for residue threshold functions 2002 IEEE International Symposium on Circuits and Systems (ISCAS)
Ponencia2002 Threshold-logic-based design of compressors ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS
Ponencia2001 A low-voltage low-power high performance fully integrated DTMF receiver European Solid-State Circuits Conference
Artículo2001 A practical floating-gate Muller-C element using vMOS threshold gates IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
Artículo2001 Efficient realization of a threshold voter for self-purging redundancy JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
Ponencia2001 Low-power logic styles for full-adder circuits ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS
Ponencia2001 Practical low-cost CPL implementations of threshold logic functions Proceedings of the IEEE Great Lakes Symposium on VLSI
Ponencia2001 Reed-Muller descriptions of symmetric functions ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Ponencia2000 Efficient νMOS realization of threshold voters for self-purging redundancy Proceedings - 13th Symposium on Integrated Circuits and Systems Design
Ponencia2000 nu MOS-based compressor designs ICM 2000: PROCEEDINGS OF THE 12TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS
Artículo2000 nu MOS-based sorter for arithmetic applications VLSI DESIGN
Artículo2000 Threshold logic based adders using floating-gate circuits Advances in Physics, Electronics and Signal Processing Applications
Ponencia1999 An algorithm for face-constrained encoding of symbols using minimum code length DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS
Ponencia1999 nu MOS-based sorters for multiplier implementations ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1
Ponencia1998 A dynamic model for the state assignment problem DESIGN, AUTOMATION AND TEST IN EUROPE, PROCEEDINGS
Artículo1998 Sorting networks implemented as vMOS circuits ELECTRONICS LETTERS
Ponencia1997 A performance-driven placement algorithm with simultaneous Place & Route optimization for analog IC's EUROPEAN DESIGN & TEST CONFERENCE - ED&TC 97, PROCEEDINGS
Artículo1997 Low-cost BSA technique for threshold-logic gate based multiplier implementations ELECTRONICS LETTERS
Ponencia1997 Performance-driven placement algorithm with simultaneous place & route optimization for analog IC's EUROPEAN DESIGN & TEST CONFERENCE - ED&TC 97, PROCEEDINGS
Letter1995 Constrained state assignment of easily testable fsms JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
Artículo1995 Low-power CMOS threshold-logic gate ELECTRONICS LETTERS
Ponencia1995 Optimum PLA folding through boolean satisfiability Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Ponencia1994 An algorithm for the place-and-route problem in the layout of analog circuits 1994 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1
Ponencia1994 Diseño eficiente de un elemento-C de Muller basado en puertas umbral CMOS Actas del IX Congreso de Diseño de Circuitos Integrados, 9, 10 y 11 de noviembre de 1994, Maspalomas, Gran Canaria
Artículo1994 FSMTEST - synthesis for testability and test-generation of PLA-based FSM IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES
Artículo1994 GELSA: una herramienta para el layout automático de circuitos analógicos Actas del IX Congreso de Diseño de Circuitos Integrados, 9, 10 y 11 de noviembre de 1994, Maspalomas, Gran Canaria
Artículo1994 Hazard-free edge-triggered d-flipflop based on threshold gates ELECTRONICS LETTERS
Corrección1994 Hazard-free edge-triggered d-flipflop based on threshold gates (vol 30, pg 1390, 1994) ELECTRONICS LETTERS
Artículo1994 State merging and state splitting via state assignment - A new FSM synthesis algorithm IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES
Ponencia1993 Easily testable PLA-based FSMS 1993 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS : PROCEEDINGS, VOLS 1-4 ( ISCAS 93 )
Ponencia1993 Un algoritmo de enumeración implícita basado en BDDS para el asignamiento óptimo de FSMS VIII Congreso Diseño de Circuitos Integrados: Málaga, 9 al 11 de noviembre de 1993
Artículo1993 Un algoritmo para la generación del layout de circuitos analógicos VIII Congreso Diseño de Circuitos Integrados: Málaga, 9 al 11 de noviembre de 1993
Artículo1993 Una herramienta para la construcción de multiplicadores óptimos en campos finitos VIII Congreso Diseño de Circuitos Integrados: Málaga, 9 al 11 de noviembre de 1993
Artículo1992 Efficient state reduction methods for PLA-based sequential circuits IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES
Ponencia1992 Sintesis para testabilidad de FSMs basadas en PLAs VII Congreso de Diseño de Circuitos Integrados: 3, 4 y 5 de noviembre de 1992, Toledo, España : actas
Artículo1992 Una aproximación al problema de layout automático de celdas analógicas VII Congreso de Diseño de Circuitos Integrados: 3, 4 y 5 de noviembre de 1992, Toledo, España : actas
Ponencia1991 SMAS: A program for the concurrent state reduction and state assignment of finite state machines Proceedings - IEEE International Symposium on Circuits and Systems
Ponencia1990 A new method for the state reduction of incompletely specified finite sequential machines Proceedings of the European Design Automation Conference, EDAC 1990
Artículo1990 Area Optimised Registers by Using a Folded PLA IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS
Ponencia1990 New approach to the state reduction in incompletely specified sequential machines 1990 IEEE INTERNATIONAL SYMP ON CIRCUITS AND SYSTEMS, VOLS 1-4
Ponencia1989 Application of chaotic switched-capacitor circuits for random number generation IEE Conference Publication
Artículo1989 Efficiency of State Assignment Methods for PLA-Based Sequential Circuits IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES
Ponencia1988 New method for the efficient state-assignment of PLA-based sequential machines Digest of technical papers - IEEE International Conference on Computer-Aided Design
Una contribucion al diseño automatico de circuitos digitales usando pla's (1987)
Dirigida por:
Tesis dirigidas/tutorizadas:5
Fecha lectura Título Rol
04/02/2011 Diseño lógico de circuitos digitales usando dispositivos con característica NDR Director/a
13/02/2009 Una aportación al diseño digital usando dispositivos basados en efecto tunel resonante Director/a
27/11/2003 Algoritmos de codificación binaria de símbolos para la síntesis lógica de circuitos integrados digitales Director/a
17/12/2001 GELSA: un colocador flexible para circuitos integrados analógicos Director/a
1992 Una aproximación al diseño óptimo de máquinas de estados finitos Director/a

Proyectos de Investigación

Fecha de inicio Fecha de fin Rol Denominación Agencia financiadora
31/01/2008 31/12/2012 Responsable Diseño e implementación de circuitos multivaluados usando dispositivos con característica Ndr (P07-TIC-02961) Junta de Andalucía - Consejería de Innovación, Ciencia y Empresas (Autonómico)
01/03/2006 28/02/2009 Investigador/a Técnicas de diseño y test de circuitos integrados mixtos en tecnologías emergentes (EXC/2005/TIC-927) Junta de Andalucía (Plan Andaluz de Investigación) (Autonómico)
01/01/2018 30/06/2021 Responsable Circuitos y Arquitecturas con Dispositivos Steep Slope para Aplicaciones de muy Bajo Consumo de Potencia (TEC2017-87052-P) Ministerio de Economía y Competitividad (Nacional)
01/01/2011 31/12/2014 Investigador/a Arquitecturas y Circuitos con Rtds para Aplicaciones Lógicas y no Lineales (TEC2010-18937) Ministerio de Ciencia e Innovación (Nacional)
01/01/2014 30/06/2018 Responsable Nano-Arquitecturas para Computación Lógica Usando Dispositivos Emergentes (TEC2013-40670-P) Ministerio de Economía y Competitividad (Nacional)
01/01/2020 30/06/2023 Investigador/a Two-Dimensional Oscillatory Neural Networks for Energy Efficent Neuromorphic computing (NeurONN) (H2020-871501) Comisión Europea (Europeo)

Contratos

Fecha de inicio Fecha de fin Rol Denominación Agencia financiadora
17/07/1998 31/12/1998 Investigador/a MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (OG-006/99)
17/07/1998 31/12/1998 Investigador/a MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (OG-007/99)
17/07/1998 31/12/1998 Investigador/a MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (OG-005/99)
17/07/1998 31/12/1998 Investigador/a MICROELECTRÓNICA: TECNOLOGÍA, DISEÑO Y TEST (OG-008/99)
03/07/2001 31/12/2001 Investigador/a Microelectrónica: tecnología, diseño y test (ESPRIT 25213 - TARDIS) (OG-021/02) Consejo Superior de Investigaciones Científicas (Instituto de Microelectrónica de Sevilla) (Desconocido)
04/01/2005 31/03/2005 Investigador/a Microelectrónica: tecnología, diseño y test (OG-122/05) Consejo Superior de Investigaciones Científicas (Desconocido)
03/07/2001 31/12/2001 Investigador/a Microelectrónica: tecnología, diseño y test (ESPRIT 33485 - MICROCARD) (OG-022/02) Consejo Superior de Investigaciones Científicas (Instituto de Microelectrónica de Sevilla) (Desconocido)
27/09/2002 31/12/2002 Investigador/a Microelectrónica: tecnología, diseño y test (OG-040/03) Consejo Superior de Investigaciones Científicas (Desconocido)
22/07/2003 31/12/2003 Investigador/a Microelectrónica: tecnología, diseño y test (OG-079/04) Consejo Superior de Investigaciones Científicas (Desconocido)
07/03/2024 30/06/2026 Investigador/a USECHIP: CÁTEDRA EN MICROELECTRÓNICA DE LA UNIVERSIDAD DE SEVILLA (TSI-069100-2023-001) Ministerio de Asuntos Económicos y Transformación Digital (Local)
El investigador no tiene ningún resultado de investigación asociado