| Ponencia | 2024 |
Hardware Secure Boot. A Review Of ”IRIS: An Embedded Secure Boot for IoT devices”
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IX Jornadas Nacionales de Investigación En Ciberseguridad |
| Ponencia | 2024 |
Metodología basada en proyectos para el desarrollo de sistemas IoT
|
XVI Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE 2024). Libro de actas: XVI Conferência em Tecnologia, Aprendizagem e Ensino da Eletrónica (TAEE 2024). Livro de atas.XVI International Conference of Technology, Learning and Teaching of Electronics (TAEE 2024). Proceedings book |
| Artículo | 2024 |
NanoBoot: A Field-Programmable Gate Array/System-on-Chip Hardware Boot Loader for IoT Devices
|
ELECTRONICS |
| Artículo | 2023 |
IRIS: an embedded secure boot for IoT devices
|
Internet of Things (Netherlands) |
| Capítulo | 2022 |
Entorno de virtualización para la realización y evaluación de prácticas de laboratorio TIC
|
Libro de actas TAEE 2022 XV Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica: Livro de procedimentos TAEE 2022 XV Conferência em Tecnologia, Aprendizagem e Ensino da Eletrónica=Proceedings book TAEE 2022 XV International Conference of Technology, Learning and Teaching of Electronics |
| Ponencia | 2022 |
Virtualization environment for IT labs development and assessment
|
15th International Conference of Technology, Learning and Teaching of Electronics, TAEE 2022 - Proceedings |
| Artículo | 2021 |
An integrated digital system design framework with on-chip functional verification and performance evaluation
|
IEEE ACCESS |
| Artículo | 2021 |
Embedded LUKS (E-LUKS): a hardware solution to IoT security
|
ELECTRONICS |
| Artículo | 2020 |
Address-encoded byte order
|
MICROPROCESSORS AND MICROSYSTEMS |
| Ponencia | 2020 |
Experiencia en la adaptación de una asignatura de máster para su impartición completa a distancia
|
XIV Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica: Proceedings TAEE2020 = XIV Conferência em Tecnologias Aplicadas ao Ensino da Eletrónica = XIV Conference on Technology, Teaching and Learning of Electronics |
| Artículo | 2020 |
Using the complement of the cosine to compute trigonometric functions
|
EURASIP JOURNAL ON ADVANCES IN SIGNAL PROCESSING |
| Artículo | 2019 |
High-performance time server core for FPGA system-on-chip
|
ELECTRONICS |
| Ponencia | 2018 |
A proposal for a new way of classifying network security metrics. Study of the information collected through a honeypot
|
2018 IEEE 18TH INTERNATIONAL CONFERENCE ON SOFTWARE QUALITY, RELIABILITY AND SECURITY COMPANION (QRS-C) |
| Artículo | 2017 |
Minimalistic SDHC-SPI hardware reader module for boot loader applications
|
MICROELECTRONICS JOURNAL |
| Capítulo | 2016 |
Metodología PBL en modo colaborativo aplicada al diseño de un SoC
|
Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE 2016): libro de Actas del XII Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica |
| Ponencia | 2014 |
Application of virtualization technology to the study of quality of service techniques
|
Proceedings of XI Tecnologias Aplicadas a la Ensenanza de la Electronica (Technologies Applied to Electronics Teaching), TAEE 2014 |
| Otros | 2013 |
Interview: Our proposal is a hardware-friendly file system suitable for embedded systems
|
ELECTRONICS LETTERS |
| Artículo | 2013 |
NanoFS: a hardware-oriented file system
|
ELECTRONICS LETTERS |
| Capítulo | 2012 |
Open Development Platform for Embedded Systems
|
Grid Computing - Technology and Applications, Widespread Coverage and New Horizons |
| Artículo | 2011 |
Fast-convergence microsecond-accurate clock discipline algorithm for hardware implementation
|
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT |
| Artículo | 2011 |
Studying the viability of static complementary metal-oxide-semiconductor gates with a large number of inputs when using separate transistor wells
|
JOURNAL OF LOW POWER ELECTRONICS |
| Artículo | 2010 |
Comprehensive analysis on the internal power dissipation of static CMOS cells in ultra-deep sub-micron technologies
|
JOURNAL OF LOW POWER ELECTRONICS |
| Ponencia | 2009 |
Delay and power consumption of static Bulk-CMOS gates using independent bodies
|
DTIS: 2009 4TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA, PROCEEDINGS |
| Ponencia | 2009 |
Implementación sobre FPGA de un cliente SNTP de bajo coste y alta precisión
|
Actas de las IX Jornadas de computación reconfigurable y aplicaciones: Universidad de Alcalá, Departamento de Electrónica, Alcalá de Henares, 9-11 septiembre, 2009 |
| Ponencia | 2009 |
Power dissipation associated to internal effect transitions in static CMOS gates
|
INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION |
| Ponencia | 2009 |
Usando Python como HDL: estudio comparativo de resultados basado en el desarrollo de un periférico real
|
Actas de las IX Jornadas de computación reconfigurable y aplicaciones: Universidad de Alcalá, Departamento de Electrónica, Alcalá de Henares, 9-11 septiembre, 2009 |
| Ponencia | 2008 |
Design and Implementation of a SNTP Client on FPGA
|
2008 IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS, VOLS 1-5 |
| Ponencia | 2008 |
Implementation of a FFT/IFFT module on FPGA: comparison of methodologies
|
2008 4TH SOUTHERN CONFERENCE ON PROGRAMMABLE LOGIC, PROCEEDINGS |
| Ponencia | 2007 |
Design of a FFT/IFFT module as an IP core suitable for embedded systems
|
2007 INTERNATIONAL SYMPOSIUM ON INDUSTRIAL EMBEDDED SYSTEMS |
| Artículo | 2007 |
Improving the performance of static CMOS gates by using independent bodies
|
JOURNAL OF LOW POWER ELECTRONICS |
| Ponencia | 2007 |
Static power consumption in CMOS gates using independent bodies
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION |
| Ponencia | 2006 |
A SoC Design Methodology for LEON2 on FPGA
|
IWS 2006: XII Taller IBERCHIP (2006). |
| Artículo | 2006 |
Accurate Logic-Level Current Estimation for Digital CMOS Circuits
|
JOURNAL OF LOW POWER ELECTRONICS |
| Artículo | 2006 |
Automated performance evaluation of skew-tolerant clocking schemes
|
International Journal of Electronics |
| Ponencia | 2006 |
Efficient design and implementation on FPGA of a MicroBlaze peripheral for processing direct electrical networks measurements
|
Industrial Embedded Systems - IES'2006 |
| Ponencia | 2005 |
Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes
|
VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2 |
| Ponencia | 2005 |
Halotis - High accurate logic timing simulator
|
2005 PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS, VOLS 1 AND 2, PROCEEDINGS |
| Artículo | 2004 |
Signal sampling based transition modeling for digital gates characterization
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN |
| Artículo | 2003 |
Computational delay models to estimate the delay of floating cubes in CMOS circuits
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN |
| Capítulo | 2003 |
Desarrollo de una aplicación del área de producción animal
|
Innovaciones docentes en la Universidad de Sevilla, curso 2001-2002: áreas de arte y humanidades, ciencias exactas y naturales, ciencias de la salud e ingeniera y tecnología |
| Ponencia | 2003 |
Internode: internal node logic computational model
|
36TH ANNUAL SIMULATION SYMPOSIUM, PROCEEDINGS |
| Ponencia | 2002 |
Characterization of normal propagation delay for delay degradation model (DDM)
|
Lecture Notes in Computer Science |
| Capítulo | 2002 |
Efficient and fast current curve estimation of CMOS digital circuits at the logic level
|
Integrated circuit design. Power and timing modeling, optimization and simulation: 12th International Workshop, PATMOS 2002, Seville, Spain, September 11 - 13, 2002 |
| Artículo | 2002 |
Measurement of the switching activity of CMOS digital circuits at the gate level
|
Lecture Notes in Computer Science |
| Ponencia | 2001 |
AUTODDM: AUTOmatic characterization tool for the Delay Degradation Model
|
ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS |
| Ponencia | 2001 |
Gate-level simulation of CMOS circuits using the IDDM model
|
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings |
| Ponencia | 2001 |
HALOTIS: High Accuracy LOgic TIming Simulator with inertial and degradation delay model
|
DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS |
| Artículo | 2001 |
Switching activity evaluation of CMOS digital circuits using logic timing simulation
|
ELECTRONICS LETTERS |
| Artículo | 2000 |
Degradation delay model extension to CMOS gates
|
INTEGRATED CIRCUIT DESIGN, PROCEEDINGS |
| Ponencia | 2000 |
Inertial and Degradation Delay Model for CMOS logic gates
|
2000 IEEE International Symposium on Circuits and Systems (ISCAS) |
