| Ponencia | 2024 |
Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher
|
Proceedings - 2024 27th Euromicro Conference on Digital System Design, DSD 2024 |
| Ponencia | 2024 |
Review of: Protecting FPGA-Based Cryptohardware Implementations from Fault Attacks Using ADCs
|
IX Jornadas Nacionales de Investigación En Ciberseguridad |
| Ponencia | 2023 |
A Security Comparison between AES-128 and AES-256 FPGA implementations against DPA attacks
|
2023 38th Conference on Design of Circuits and Integrated Systems, DCIS 2023 |
| Ponencia | 2022 |
Automated experimental setup for EM cartography to enhance EM attacks
|
37th edition of the Conference on Design of Circuits and Integrated Systems (DCIS 2022) |
| Artículo | 2022 |
Design and evaluation of countermeasures against fault injection attacks and power side-channel leakage exploration for AES block cipher
|
IEEE ACCESS |
| Artículo | 2022 |
Gate-level design methodology for side-channel resistant logic styles using TFETs
|
IEEE Embedded Systems Letters |
| Artículo | 2022 |
Gate-level hardware countermeasure comparison against power analysis attacks
|
APPLIED SCIENCES-BASEL |
| Artículo | 2022 |
Hardware countermeasures benchmarking against fault attacks
|
APPLIED SCIENCES-BASEL |
| Artículo | 2021 |
Design and analysis of secure emerging crypto-hardware using HyperFET devices
|
IEEE Transactions on Emerging Topics in Computing |
| Ponencia | 2020 |
Hamming-code based fault detection design methodology for block ciphers
|
Proceedings - IEEE International Symposium on Circuits and Systems |
| Artículo | 2020 |
Projection of dual-rail dpa countermeasures in future finfet and emerging tfet technologies
|
ACM Journal on Emerging Technologies in Computing Systems |
| Ponencia | 2019 |
Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits
|
Proceedings - 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018 |
| Libro | 2019 |
La nanotecnología: el mundo de las máquinas a escala nanométrica
|
La nanotecnología: el mundo de las máquinas a escala nanométrica |
| Artículo | 2019 |
Logic minimization and wide fan-in issues in DPL-based cryptocircuits against power analysis attacks
|
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS |
| Ponencia | 2018 |
Effect of temperature variation in experimental DPA and DEMA attacks
|
2018 28TH INTERNATIONAL SYMPOSIUM ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS) |
| Artículo | 2017 |
Embedded electronic circuits for cryptography, hardware security and true random number generation: an overview
|
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS |
| Editorial | 2017 |
Guest Editorial "Secure lightweight crypto-hardware"
|
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS |
| Artículo | 2017 |
Power and energy issues on lightweight cryptography
|
JOURNAL OF LOW POWER ELECTRONICS |
| Ponencia | 2017 |
Secure cryptographic hardware implementation issues for high-performance applications
|
Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016 |
| Artículo | 2016 |
Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions
|
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS |
| Ponencia | 2016 |
Diseño de circuitos integrados y seguridad de circuitos criptográficos frente a ataques
|
III Jornada de investigación y postgrado: Libro de Actas |
| Ponencia | 2016 |
Experience of implementation and development of an online Master in Microelectronics
|
Proceedings of 2016 Technologies Applied to Electronics Teaching, TAEE 2016 |
| Capítulo | 2016 |
Experiencia de puesta en marcha y desarrollo de un Máster on-line en Microelectrónica
|
Tecnología, Aprendizaje y Enseñanza de la Electrónica (TAEE 2016): libro de Actas del XII Congreso de Tecnología, Aprendizaje y Enseñanza de la Electrónica |
| Libro | 2016 |
La nanotecnología: explorando un cosmos en miniatura
|
La nanotecnología: explorando un cosmos en miniatura |
| Ponencia | 2016 |
Optimized DPA attack on Trivium stream cipher using correlation shape distinguishers
|
2015 Conference on Design of Circuits and Integrated Systems, DCIS 2015 |
| Ponencia | 2015 |
DPA vulnerability analysis on Trivium stream cipher using an optimized power model
|
2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
| Ponencia | 2015 |
Programmable ASICs for Model Predictive Control
|
2015 IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL TECHNOLOGY (ICIT) |
| Artículo | 2014 |
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits
|
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS |
| Ponencia | 2014 |
Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications
|
2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014 |
| Ponencia | 2014 |
Low-Power Differential Logic Gates for DPA Resistant Circuits
|
2014 17TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD) |
| Artículo | 2013 |
A programmable and configurable ASIC to generate piecewise-affine functions defined over general partitions
|
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS |
| Ponencia | 2013 |
Automatic and systematic control of experimental data measurements on ASICs
|
|
| Artículo | 2012 |
An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors
|
IEEE JOURNAL OF SOLID-STATE CIRCUITS |
| Ponencia | 2012 |
ASIC-in-the-loop methodology for verification of piecewise affine controllers
|
2012 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS) |
| Artículo | 2011 |
A 32 x 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput
|
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS |
| Ponencia | 2010 |
An Improved Differential Pull-down Network Logic Configuration for DPA Resistant Circuits
|
2010 INTERNATIONAL CONFERENCE ON MICROELECTRONICS |
| Ponencia | 2010 |
Optimization of clock-gating Structures for low-leakage high-performance Applications
|
2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS |
| Ponencia | 2010 |
Switching noise optimization in the wake-up phase of leakage-aware power gating structures
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION |
| Ponencia | 2010 |
Using physical unclonable functions for hardware authentication: a survey
|
Proceedings XXV Conference on Design of Circuits and Integrated Systems (2010) |
| Artículo | 2009 |
CAVIAR: a 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking
|
IEEE TRANSACTIONS ON NEURAL NETWORKS |
| Ponencia | 2008 |
A 1.2V 5.14mW Quadrature Frequency Synthesizer in 90nm CMOS Technology for 2.4GHz ZigBee Applications
|
2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4 |
| Ponencia | 2008 |
A 2.5MHz bandpass active complex filter With 2.4MHz bandwidth for wireless communications
|
23rd Conference on Design of Circuits and Integrated Systems (2008) |
| Ponencia | 2008 |
Fully digital AER convolution chip for vision processing
|
PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 |
| Ponencia | 2008 |
Geometry optimization in basic CMOS cells for improved power, leakage, and noise performances
|
Proceedings - International Conference on Advances in Electronics and Micro-electronics, ENICS 2008 |
| Ponencia | 2008 |
La simulación eléctrica en el trabajo académicamente dirigido como vehículo docente para la enseñanza de la electrónica
|
VIII Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica (2008) |
| Artículo | 2008 |
On real-time AER 2-D convolutions hardware for neuromorphic spike-based cortical processing
|
IEEE TRANSACTIONS ON NEURAL NETWORKS |
| Ponencia | 2007 |
A methodology for switching noise estimation at gate level
|
VLSI CIRCUITS AND SYSTEMS III |
| Ponencia | 2007 |
A switching noise vision of the optimization techniques for low-power synthesis
|
2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3 |
| Ponencia | 2007 |
Asymmetric clock driver for improved power and noise performances
|
2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 |
| Ponencia | 2007 |
Asynchronous staggered set/reset techniques for low-noise applications
|
2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 |
| Ponencia | 2007 |
Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits
|
VLSI CIRCUITS AND SYSTEMS III |
| Ponencia | 2007 |
Spike events processing for vision systems
|
2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 |
| Ponencia | 2006 |
A bio-inspired event-based real-time image processor
|
Proceedings of the First IEEE/RAS-EMBS International Conference on Biomedical Robotics and Biomechatronics, 2006, BioRob 2006 |
| Artículo | 2006 |
A neuromorphic cortical-layer microchip for spike-based event processing vision systems
|
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS |
| Ponencia | 2006 |
An arbitrary kernel convolution AER- transceiver chip for real-time image filtering
|
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS |
| Ponencia | 2006 |
High-speed image processing with AER-based components
|
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS |
| Artículo | 2006 |
Optimization of master-slave flip-flops for high-performance applications
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION |
| Ponencia | 2005 |
A digital pixel cell for address event representation image convolution processing
|
BIOENGINEERED AND BIOINSPIRED SYSTEMS II |
| Artículo | 2005 |
A mixed-signal integrated circuit for FM-DCSK modulation
|
IEEE JOURNAL OF SOLID-STATE CIRCUITS |
| Ponencia | 2005 |
AER building blocks for multi-layer multi-chip neuromorphic vision systems
|
Advances in Neural Information Processing Systems |
| Ponencia | 2005 |
Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits
|
VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2 |
| Ponencia | 2005 |
Performance analysis of full adders in CMOS technologies
|
VLSI CIRCUITS AND SYSTEMS II, PTS 1 AND 2 |
| Artículo | 2005 |
Selective Clock-Gating for Low-Power Synchronous Counters
|
JOURNAL OF LOW POWER ELECTRONICS |
| Ponencia | 2004 |
A mixed-signal integrated circuit for FM-DCSK modulation
|
ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE |
| Artículo | 2003 |
A new hybrid CBL-CMOS cell for optimum noise/power application
|
INTEGRATED CIRCUIT AND SYSTEM DESIGN |
| Ponencia | 2003 |
Analysis of current-mode flip-flops in CMOS technologies
|
VLSI CIRCUITS AND SYSTEMS |
| Ponencia | 2003 |
Switching noise reduction in clock distribution in mixed-mode VLSI circuits
|
VLSI CIRCUITS AND SYSTEMS |
| Artículo | 2002 |
A technique to generate CMOS VLSI flip-flops based on differential latches
|
Lecture Notes in Computer Science |
| Artículo | 2002 |
Analysis of high-performance flip-flops for submicron mixed-signal applications
|
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING |
| Artículo | 2002 |
High-performance edge-triggered flip-flops using weak-branch differential latch
|
ELECTRONICS LETTERS |
| Editorial | 2002 |
Preface
|
Lecture Notes in Computer Science |
| Artículo | 2002 |
Selective clock-gating for low power/low noise synchronous counters
|
Lecture Notes in Computer Science |
| Artículo | 2002 |
VHDL behavioural modelling of pipeline analog to digital converters
|
MEASUREMENT |
| Ponencia | 2001 |
Analog/mixed-signal IP modeling for design reuse
|
DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS |
| Ponencia | 2001 |
Gate-level simulation of CMOS circuits using the IDDM model
|
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings |
| Ponencia | 2001 |
HALOTIS: High Accuracy LOgic TIming Simulator with inertial and degradation delay model
|
DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS |
| Ponencia | 2000 |
A mixed-signal CMOS MODEM ASIC for data transmission on the low-voltage power-line with sensitivity of 283μVrms at 10Kbps
|
European Solid-State Circuits Conference |
| Ponencia | 2000 |
A VHDL-based methodology for the design and verification of pipeline A/D converters
|
Design Automation and Test in Europe Conference and Exhibition |
| Ponencia | 2000 |
An application of self-timed circuits to the reduction of switching noise in analog-digital circuits
|
INTEGRATED CIRCUIT DESIGN, PROCEEDINGS |
| Artículo | 2000 |
Degradation delay model extension to CMOS gates
|
INTEGRATED CIRCUIT DESIGN, PROCEEDINGS |
| Ponencia | 2000 |
Inertial and Degradation Delay Model for CMOS logic gates
|
2000 IEEE International Symposium on Circuits and Systems (ISCAS) |
| Artículo | 2000 |
Influence of clocking strategies on the design of low switching-noise digital and mixed-signal VLSI circuits
|
INTEGRATED CIRCUIT DESIGN, PROCEEDINGS |
| Artículo | 2000 |
Logical modelling of delay degradation effect in static CMOS gates
|
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS |
| Libro | 2000 |
Temporización en circuitos integrados digitales CMOS
|
Temporización en circuitos integrados digitales CMOS |
| Ponencia | 2000 |
VHDL-based behavioural description of pipeline ADCs
|
ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL IV |
| Artículo | 1999 |
Inertial effect handling method for CMOS digital IC simulation
|
ELECTRONICS LETTERS |
| Artículo | 1999 |
Self-timed boundary-scan cells for multi-chip module test
|
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS |
| Ponencia | 1998 |
Clock switching: A new Design for current Testability (DcT) method for dynamic logic circuits
|
1998 IEEE INTERNATIONAL WORKSHOP ON IDDQ TESTING, PROCEEDINGS |
| Artículo | 1998 |
Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure
|
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS |
| Artículo | 1998 |
Efficient self-timed circuits based on weak NMOS-trees
|
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems |
| Ponencia | 1998 |
Self-timed boundary-scan cells for multi-chip module test
|
16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS |
| Artículo | 1997 |
A single, double lumen high-flow catheter for patients undergoing peripheral blood stem cell transplantation. Experience at the National Cancer Institute in Mexico
|
BONE MARROW TRANSPLANTATION |
| Artículo | 1997 |
Analysis of metastable operation in a CMOS dynamic D-latch
|
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING |
| Artículo | 1997 |
CMOS inverter maximum frequency of operation due to digital signal degradation
|
ELECTRONICS LETTERS |
| Artículo | 1995 |
Evaluation of metastability transfer models - an application to an n-bistable CMOS synchronizer
|
International Journal of Electronics |
| Nota | 1995 |
Modular asynchronous arbiter insensitive to metastability
|
IEEE TRANSACTIONS ON COMPUTERS |
| Ponencia | 1995 |
New CMOS VLSI linear self-timed architectures
|
SECOND WORKING CONFERENCE ON ASYNCHRONOUS DESIGN METHODOLOGIES, PROCEEDINGS |
| Nota | 1995 |
SODS - a new cmos differential-type structure
|
IEEE JOURNAL OF SOLID-STATE CIRCUITS |
| Ponencia | 1994 |
Implementación de FIFOs mediante arquitecturas lineales autotemporizadas VLSI
|
Actas del IX Congreso de Diseño de Circuitos Integrados, 9, 10 y 11 de noviembre de 1994, Maspalomas, Gran Canaria |
| Ponencia | 1994 |
Modelos de retraso dinámicos para puertas estáticas CMOS: (basados en la propagación de pulsos)
|
Actas del IX Congreso de Diseño de Circuitos Integrados, 9, 10 y 11 de noviembre de 1994, Maspalomas, Gran Canaria |
| Ponencia | 1993 |
A new faster method for calculating the resolution coefficient of CMOS latches: Design of an optimum latch
|
1993 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS : PROCEEDINGS, VOLS 1-4 ( ISCAS 93 ) |
| Artículo | 1993 |
Arquitectura para el diseño de circuitos autotemporizados bidimensionales. Realización de multiplicadores
|
VIII Congreso Diseño de Circuitos Integrados: Málaga, 9 al 11 de noviembre de 1993 |
| Artículo | 1993 |
Design, testing and applications of 4-valued pads
|
International Journal of Electronics |
| Ponencia | 1993 |
Fully Digital Redundant Random Number Generator in CMOS Technology
|
ESSCIRC '93: NINETEENTH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS |
| Ponencia | 1993 |
Modeling of real bistables in VHDL
|
EURO-DAC 93 - EUROPEAN DESIGN AUTOMATION CONFERENCE WITH EURO-VHDL 93 : PROCEEDINGS |
| Artículo | 1993 |
Un nuevo modelo de retraso para puertas lógicas CMOS
|
VIII Congreso Diseño de Circuitos Integrados: Málaga, 9 al 11 de noviembre de 1993 |
| Ponencia | 1993 |
Workbench for generation of component models
|
European Design Automation Conference - Proceedings |
| Ponencia | 1992 |
A simple binary random number generator: new approaches for CMOS VLSI
|
PROCEEDINGS OF THE 35TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 |
| Ponencia | 1992 |
Determinación de coeficienta de resolución en biestables RS CMOS
|
VII Congreso de Diseño de Circuitos Integrados: 3, 4 y 5 de noviembre de 1992, Toledo, España : actas |
| Ponencia | 1992 |
Metodología de diseño de circuitos integrados VLSI
|
VII Congreso de Diseño de Circuitos Integrados: 3, 4 y 5 de noviembre de 1992, Toledo, España : actas |
| Artículo | 1992 |
Multiple-valued pads for binary chips
|
ELECTRONICS LETTERS |
| Artículo | 1992 |
Simple binary random number generator
|
ELECTRONICS LETTERS |
| Ponencia | 1991 |
Diseño de una familia de pads
|
Diseño de circuitos integrados: actas del VI Congreso, Santander, 11/15 de noviembre de 1991 |
